ASIC Digital Design, Sr Engineer

Synopsys

Wuhan, Hubei
Permanent
Full-time

20 days ago

Job Description and RequirementsASIC Verification EngineerOur DDR PHY IP team is looking to add a Digital ASIC Verification Engineer to our team. In this role you will be responsible for developing test benches and verifying integrated IP Subsystems for our global customers.Key Qualifications

BSEE in EE with 3+ years of relevant experience or MSEE with 1+ years of relevant experience
Experience in ASIC RTL design and verification at the chip level and block level
Strong Verilog, system Verilog, UVM, PERL, and TCL skills
Knowledge in silicon debugging
Demonstrates good communication skills in both Mandarin and English
Demonstrates good analysis and problem-solving skills
Knowledge of high speed interface protocols is a plus
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

Hire TypeEmployeeJob CategoryEngineeringJob SubcategoryASIC Digital Design

Synopsys

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