ASIC Digital Design, Staff Engineer
Synopsys
- Wuhan, Hubei
- Permanent
- Full-time
Seeking a highly motivated and innovative Digital Verification Engineer with a proven theoretical and practical background in high-speed interface IPs.The position offers an excellent opportunity to work with an adept team of digital and mixed-signal engineers responsible for delivering high-end next-generation PAM4 and NRZ SERDES products spanning multiple protocols like Ethernet and PCIe6Duties & Responsibilities
- Defining verification plans and building verification environments for chip/module level designs using System Verilog with UVM.
- Applying advanced verification techniques like constrained random test generation, functional coverage, assertions and formal verification.
- Writing test cases, checkers, and coverage that implement the verification test plan.
- Bachelors / Masters in Electrical or Computer Engineering
- RTL verification using coverage driven verification techniques
- Scripting and C/C++ coding skills
- Proficient in HDL languages System Verilog, Verilog
- Good analytical, oral, and written communication skills
- Able to write clean, readable, and maintainable code
- Self-motivated, proactive team player
- Experience or academic knowledge of the design/verification of interfaces and controllers for high-speed serial protocols such as PCI-Express, CXL, or SAS/SATA
- Understanding of ASIC designs and verification methodologies
- To grow and manage verification of product end-to-end.
- Cross-functional learning and interaction with professional teams across domains and geographies.
- Customer-facing role working in close collaboration with pre and post-sales team
- Develop systematic ways to address new problems, think outside of the box
- Have an impact on the new product architectures, quality and development strategies