ASIC Digital Design, Staff Engineer
Synopsys
- Wuhan, Hubei
- Permanent
- Full-time
BSEE with 8+ years or MSEE with 5+ years of relevant experience in the industry
Good experience in preparing verification strategy and writing block-level test-cases including constrained directed random tests
Must have good knowledge of scripting in Shell, Perl, Python and TCL is a plus
Should have good understanding on ASIC design (connecting modules, simple coding style, etc.)
Theoretical and practical background in LPDDR/DDR memory is a solid plus
Knowledge of high-speed interface protocols, such as CHI, AXI, AHB, DFI, is a solid plus
Resolves issues in clever ways and exercises impartial judgment in selecting methods and techniques to obtain solutions
Must be self-motivated, proactive, and able to guarantee good design quality while meeting tight deadlines
May guide more junior peers with aspects of their job. Networks with senior internal and external personnel in own area of expertise
Good communication skills for interacting between different groupsPreferred Experience
Defining verification strategy and writing test plan with high quality
Building complex testbench and writing test-cases in System Verilog
Debugging failure and collecting coverage to fulfill feature verification requirement
Interacting with Application Engineers for customer supportInclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.Hire TypeEmployeeJob CategoryEngineeringJob SubcategoryASIC Digital Design