2026 Campus - SoC DFT Engineer

• Proficiency in whole DFT architecture definition.

• Setup and maintain DFT flow, familiar with script language.

• Be responsible for definition and implementation different schemes of DFT aspects: including scan/MBIST/JTAG insertion, ATPG generation, test patterns generation.

• Experience RTL/netlist simulation, good debug capability, familiar with Verilog.

• Experience with ATE on-line debugging and DFT diagnosis. Experience with Post-silicon DPPM improvement, coverage hole analysis.

• Bachelor or master’s degree in Microelectronics, Electronics, Electrical Engineering, Computer Science or relevant disciplines.
• Good knowledge and experience in DFT implementation methodology, flow optimization and DFT coverage improvement. Mentor tool is a plus.
• Strong skills of solving problem, self-motivated and good team player.

NXP Semiconductors