Verification Eng Intern
Lattice Semiconductor
- Shanghai
- Training
- Full-time
- Work with other verification engineers on IP level and Sub-system verifications.
- Created UVM based test cases to meet coverage goals.
- Optimize scripts to improve team work efficiencies.
- MSc in EE or relevant subjects.
- Course work project experiences on Verilog, system Verilog is preferred.
- Can write and read in English for project work.