Setup and maintain DFT flow, familiar with script language.
Be responsible for definition and implementation different schemes of DFT aspects: including scan/MBIST/JTAG insertion, ATPG generation, test patterns generation.
Experience RTL/netlist simulation, good debug capability , familiar with Verilog.
Requirements:
Bachelor or master’s degree in Microelectronics, Electronics, Electrical Engineering, Computer Science or relevant disciplines
Good knowledge and experience in DFT implementation methodology, flow optimization and DFT coverage improvement. Simens tool is a plus.
Strong problem solving skills, self-motivated and good team player.
