2026 Intern - SoC RTL Design and Integration

• Work on SOC Front-end design team, be responsible for the SOC subsystem design, including subsystem integration, RTL coding, design rule check and constrain delivery.

• Strong Verilog and C coding skills
• Knowledge of on-chip bus protocols: AMBA, AXI or similar is a plus
• Extensive knowledge and experience in front-end implementation tasks such as constraint definition (timing & power), synthesis, power analysis, equivalence checking and STA is a plus
• Good English communication skills.

NXP Semiconductors