
NPU SRIOV FET Leader
- Shanghai
- Permanent
- Full-time
- Pre-Silicon:
- SRIOV feature list & IPSE test plan creation & Execution.
- Collaborating with emulation team for emulation task to reduce post silicon risks.
- Collaborating with diag team for diag tool development.
- IP & System validation test plan review and approvement. Coordinates over all platform test coverage &strategy.
- Post-Silicon:
- BU & collaborating with various team(HW, BIOS, FW, diag, SW etc) for IP feature enablement & solution delivery
- IP issue debug and issue End-To-End drive as FET leader.
- Customer issue technical support.
- Knowledge of X86 computer hardware architecture
- Knowledge of both Linux and windows
- Understand the architecture and algorithm of the SRIOV
- Understand the architecture and algorithm of the NPU
- Familiar with PCIe, VFIO, IOMMU, security isolation techniques
- Experience developing/executing BU and feature validation test plan, debug skills required.
- FPGA&ASIC development experience preferred
- Excellent verbal and written English communication skills
- Team leader/Project leader experience preferred
- Working knowledge of lab equipment
- Forward thinker to improve process and drive innovation
- Scripting and automation tool development skills a plus
- Master with 5+ years’ experience or Bachelor with 8+ years’ experience, minimum 2 years’ experience focus on SRIOV or NPU
- Electronic and Computer Sciences or related Majors