MTS Silicon Design Engineer
Advanced Micro Devices
- Shanghai
- Permanent
- Full-time
- Responsible for Front-End chip implementation including design, implementation and execution of the flow that starts with RTL code and ends with the delivery of a netlist package ready for physical design
- Responsible for ASIC design methodology and flow development, interfacing with EDA vendors on technology
- Responsible for cdc/lint, timing closure, lower power implementation and netlist quality check with RTL designer and PD team
- MS degree of EE, 7~10 years working experience
- Experience with Verilog RTL design/implementation and has experience of large digital ASIC project
- Experience with front-end EDA tools and flows (Fusion compiler, PrimeTime, Conformal, VSI/VCLP, Formality/LEC, etc…)
- Experience with unix/linux and scripts (tcl, perl, etc.)
- Experience with physical design is a plus
- Has Synthesis or physical implement experience
- Experience with lower power design methodology
- Good English skills on talking, presentation and writing documents
- Good communication and strong sense of responsibility, task scheduling, and time management
- Masters degree in Micro Electronics/ Integrated Circuit Science, or related field preferred