Design Engineer II (Middle-end)
Cadence Design Systems View all jobs
- Nanjing, Jiangsu
- Permanent
- Full-time
- Drive middle-end design activities including synthesis, DFT, STA, ECO, and signoff for IP development projects.
- Support implementation and signoff work for advanced IP programs, including eUSB2v2 and UCIe AP/SP developments across multiple technology nodes.
- Perform timing analysis and closure across different modes and corners, and support efficient ECO convergence.
- Collaborate with front-end design, verification, physical design, DFT, and other cross-functional teams to ensure smooth project execution.
- Develop, maintain, and optimize design flows, checks, and automation to improve QoR, robustness, and execution efficiency.
- Participate in signoff quality review and issue resolution to ensure tapeout readiness.
- Explore and apply AI/LLM-assisted methodologies to improve debug efficiency, workflow automation, and engineering productivity.
- Identify opportunities to enhance the end-to-end IP development process through scripting, intelligent automation, and methodology improvement.
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Microelectronics, or a related field.
- Solid understanding of digital IC design and development flow.
- Hands-on experience in one or more of the following areas: digital design, synthesis, DFT, STA, ECO, and signoff.
- Familiarity with mainstream EDA tools and digital design/middle-end/signoff methodologies.
- Experience with scripting and automation, such as Tcl, Python, Perl, or Shell, is strongly preferred.
- Strong interest in applying AI technologies to semiconductor design workflows.
- Strong analytical and problem-solving skills with attention to detail.
- Good communication and teamwork skills, with the ability to work effectively across functions in a fast-paced development environment.