Sr Staff Verification Engineer ( 数字验证工程师)
Renesas Electronics View all jobs
- Shanghai
- Permanent
- Full-time
- Understanding the expected functionality of designs.
- Designing and developing verification environment
- Improve the verification architecture and flow
- Running RTL and gate-level simulations/regression.
- Code/functional coverage development, analysis and closure.
- Bachelor degree or master degree in CS/ME.
- Minimum of 8 years' experience.
- Candidate should be familiar with as System Verilog, UVM verification.
- Have Verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.).
- Independent and self-managing.
- Familiar with UVM source code or key UVM mechanism
- Familiar with industry standard verification tools and flow.
- Familiar with basic computer architecture
- Good IC verification skills and basic knowledge of logic and circuit design, good communication and problem solving skills.
- Scripting and automation skills (python) is a plus.
- Familiar with C/C++/Java or any object orientation program language, knowledge of software design pattern is a plus
- Has experience of setup over 100K lines verification environment
- Knowledge of DDR protocol is a plus.
- Knowledge of Mixed signal verification is a plus
- Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things.
- Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people's lives easier, safe and secure.
- Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day.