Lead Application Engineer - Emulation
Cadence Design Systems View all jobs
- Beijing
- Permanent
- Full-time
- Requires a BS-EE/CE (MS-EE/CE preferred) with 3-7 years of experience in design and/or verification of complex digital designs, or Applications engineering/technical support role.
- Strong knowledge of design debug techniques and a strong understanding in logic design.
- Knowledgeable in verification methodologies for complex EDA environments.
- Proficiency in HDL language like Verilog, System Verilog and VHDL. Ability to create test cases to replicate customer issues quickly.
- Proficiency in Unix/Linux scripting languages (ksh/bash/csh/perl).
- Experience with emulation, Cadence's Palladium product preferred.
- General knowledge in TBA, Coverage/Assertion flow, Low Power(UPF). UVM experience is a plus.
- Excellent communication skills. Have ability to communicate complex issue to internal teams and customers in a clear and concise manner.