Senior Staff / Staff HV IBC System Application Engineer_7134

• System Architecture & Protection Concept Definition

• Define end-to-end system architecture for HV IBC platforms (±400 V / 800 V input to intermediate bus) targeting AI rack power trees.
• Define protection concepts and thresholds (OVP/UVP/OCP/SCP/OTP, in rush management, pre-charge/discharge, isolation monitoring, fault latching/auto-retry behavior).
• Specify sensing strategy (HV bus, output current, temperature, isolation) including accuracy, bandwidth, placement, and redundancy.
• Translate AI rack requirements (power density, hot-swap behavior, redundancy, telemetry needs, serviceability) into converter-level requirements.

• Select and evaluate suitable topologies (LLC, PSFB, DAB) based on efficiency, controll ability, magnetics complexity, ZVS range, and isolation needs.
• Perform loss breakdown (switching/conduction/magnetics/capacitor/gate-drive) and thermal modeling to predict junction and hotspot temperatures.
• Build and present efficiency maps across input voltage and load, using representative AI GPU load profiles (fast transients, load steps, bursty workloads, high utilization).
• Support component selection tradeoffs (Si/SiC/GaN devices, magnetics, capacitors, current sensing, isolation components) and derating strategy.

• Conduct schematic reviews emphasizing gate-drive robustness, sensing fidelity (Kelvin connections), protection hardware, isolation strategy, and service/debug access.
• Review PCB layout with focus on:
• hot-loop minimization and controlled commutation paths
• dv/dt control, switch-node containment, and return path integrity
• creepage/clearance, isolation barriers, Y-cap placement, and safety spacing
• current sharing / paralleling considerations where applicable
• Provide actionable layout recommendations and review checklist sign-off for design iterations.

• Define EMI mitigation strategies at circuit and layout level (filter partitioning, CM/DM paths, shielding/guarding, snubbers/clamps, spread-spectrum considerations where applicable).
• Provide gate-drive recommendations (drive strength, deadtime, Miller management, negative gate bias as needed, desat/OC protection coordination).
• Support lab debug and issue resolution with customers and internal teams using scope/probing best practices, power analyzers, EMI receivers, and thermal tools.
• Perform structured root-cause analysis on field/customer issues (efficiency shortfall, thermal margin, EMI failures, false trips, oscillations, component overstress) and drive corrective actions.

• Generate system-level design guidelines for HV bus integration into AI racks (interconnect, grounding, shielding, sequencing, pre-charge, fault handling, measurement points).
• Define bring-up procedures, safe operating envelopes, and trouble shooting flows for applications teams and customers.
• Drive closure of field issues through clear action plans, validation evidence, and design/process updates.

• Support production considerations: test hooks, calibration strategy for sensing/telemetry, compliance data capture, and system-level diagnostics.
• Contribute to internal knowledge base: application notes, checklists, reference designs, and lessons learned from customer deployments.

• BSEE/MSEE in Electrical Engineering (or related).
• Experience in isolated high-power DC/DC systems and system-level application engineering (HV IBC experience strongly preferred).
• Strong understanding of power converter topologies (LLC/PSFB/DAB), magnetics, loss mechanisms, thermal design, and EMI/EMC.
• Hands-on ability to review schematics/layout and debug hardware in the lab.
• Customer-facing capability: structured communication, issue triage, and driving topics to closure under time pressure.

Infineon